So, to salvage YMTC's claim that they made kinda sorta quasi pseudo 3D NAND, you are going to focus on my casual usage of the word 'dies' despite me posting a source that explained what YMTC did in a little more detail. Sure, you win. I was kinda sorta quasi pseudo 'wrong'.
Hahahahah you don't know jackshit and just got busted mate.
He clearly doesn't know what he is talking about, I read through his shit and he says we were using 2 dies and bonding it then I was thinking 128 layers? Seriously dumbfckno, you said they stacked dies. the only way to stack dies with electrical conductivity is wafer bonding or 3D packaging with TSV. so you implied that YMTC's 128 layer NAND was made by wafer bonding or 3D packaging 128 dies.
all those memory arrays are stacked dies? each single line is 1 die stack? lmao omg.
This guy is a dumb piece of shit.no, you said they stacked dies. the only way to stack dies with electrical conductivity is wafer bonding or 3D packaging with TSV. so you implied that YMTC's 128 layer NAND was made by wafer bonding or 3D packaging 128 dies.
all those memory arrays are stacked dies? each single line is 1 die stack? lmao omg.
He faked his professional and brag about working in semi con. Clearly he is an imposter.
As if YOU know what you are talking about.
And clearly you do not know how to use internet search.
Wafer bonding I/O circuits to NAND array isn't what you meant by "stacking dies to create pseudo 3D NAND", because the memory array is actually 3D, nothing pseudo about it.And clearly you do not know how to use internet search.
The YMTC 512Gb 128L Xtacking 2.0 TLC chip size is 60.42mm², and the bit density has increased to 8.48Gb/mm², which is 92% higher than the Xtacking 1.0 chip (256Gb). Since YMTC Xtacking hybrid bonding technology uses two wafers to integrate 3D NAND devices, we can find two dies, one for NAND array chips and the other for CMOS peripheral chips.
Important: The INDENTED paragraph is NOT my words.
Yah and do you know what YMTC is doing? LololAs if YOU know what you are talking about.
China better start telling the industry they cannot use the words 'CMOS' and 'dies' together.
Carrier wafer with embedded CMOS dies.
You see he doesn't know what he is talking about.
Yes I saw him typing that too. Fcker is bullshiting.And clearly you do not know how to use internet search.
The YMTC 512Gb 128L Xtacking 2.0 TLC chip size is 60.42mm², and the bit density has increased to 8.48Gb/mm², which is 92% higher than the Xtacking 1.0 chip (256Gb). Since YMTC Xtacking hybrid bonding technology uses two wafers to integrate 3D NAND devices, we can find two dies, one for NAND array chips and the other for CMOS peripheral chips.
Important: The INDENTED paragraph is NOT my words.
US. These are mixed signal/analog chips. Texas Instruments, Analog Devices and Microchip are still the kings.
You do know YMTC branded it as 'XSTACKING', right?
Better than you will ever be able to.
Yup copy pasting shit but someone caught you bullshiting. Lolololol lolol. Dude stop embarrassing yourself.Better than you will ever be able to.
Here is YMTC's illustration of their pseudo 3D NAND product.
The problem here is that die stacking is nothing new, even dissimilar products can be, and have been, joined to perform unique tasks for niche applications. Here is a NOR die stacked atop a NAND die and both are packaged together.
So to start, YMTC did not really innovate anything new. But going back to YMTC. What make YMTC's pseudo 3D NAND more expensive to produce is that it takes up two production lines: CMOS array and memory array.
Logistically, the first question involves wafer size. Which is 200 mm? Which is 300 mm? Is both 200 mm? Or is both 300 mm? Or is it one of each? If YMTC must use both 200 mm and 300 mm wafers, which array get the 300 mm wafer? Can YOU make even an educated guess?
Here is an example of a wafer map.
In order to mate the CMOS and the memory arrays together, their dies' geographical boundaries must be identical. Maybe some allowances for slight differences to accommodate physical bonding, but at the μm level, any physical differences are irrelevant to the discussion. So what this mean, in reference to the wafer map example, is that the two product lines must be carefully managed as they progress thru the fab, post fab, and to BackEnd (BE) for extraction. If one line must use the 200 mm wafer, the tooling for that line will be different than the 300 mm wafer tools, and that will complicate the manufacturing lines even more.
Even though NAND and CMOS are established products, there are always manufacturing flaws, so not every die on a wafer will be shippable. Most edge dies are malformed dies, and those that are full formed, quite often because of them being edge dies, they often have inferior performance than dies on the main areas of the wafer. For example, a 300 mm wafer may produce 500 prime dies and a 200 mm wafer may produce 200 prime dies, now logistics is complicated even more to keep track of how many 200 mm wafers to how many 300 mm wafers in order to produce X number of final stacked pseudo 3D NAND packages. If both lines are 200 mm wafer or 300 mm wafer, then this complication would be dramatically reduced. That is not to say that YMTC was not creative. They were. But hardly 'groundbreaking'.
Already, I have at least %75 understanding of how YMTC did it. I would make a good ProcEng or TestEng for them.
That is a 26 yrs old SRAM 200 mm wafer atop some 64gb 300 mm NAND wafers. All of them are functionally dead. The NAND wafers were 'killed' by me personally for a special project that involved some important entities outside the normal customers list. Ain't that hard to make a fool out of you, little man.
The advantage is in density as shown in the teardown, being able to separately optimize production for each wafer, and being able to outsource the CMOS dies to a foundry so they can dedicate more productive capability to their core IP of the NAND array. It also has thermal budget advantages.Better than you will ever be able to.
Here is YMTC's illustration of their pseudo 3D NAND product.
The problem here is that die stacking is nothing new, even dissimilar products can be, and have been, joined to perform unique tasks for niche applications. Here is a NOR die stacked atop a NAND die and both are packaged together.
So to start, YMTC did not really innovate anything new. But going back to YMTC. What make YMTC's pseudo 3D NAND more expensive to produce is that it takes up two production lines: CMOS array and memory array.
Logistically, the first question involves wafer size. Which is 200 mm? Which is 300 mm? Is both 200 mm? Or is both 300 mm? Or is it one of each? If YMTC must use both 200 mm and 300 mm wafers, which array get the 300 mm wafer? Can YOU make even an educated guess?
Here is an example of a wafer map.
In order to mate the CMOS and the memory arrays together, their dies' geographical boundaries must be identical. Maybe some allowances for slight differences to accommodate physical bonding, but at the μm level, any physical differences are irrelevant to the discussion. So what this mean, in reference to the wafer map example, is that the two product lines must be carefully managed as they progress thru the fab, post fab, and to BackEnd (BE) for extraction. If one line must use the 200 mm wafer, the tooling for that line will be different than the 300 mm wafer tools, and that will complicate the manufacturing lines even more.
Even though NAND and CMOS are established products, there are always manufacturing flaws, so not every die on a wafer will be shippable. Most edge dies are malformed dies, and those that are full formed, quite often because of them being edge dies, they often have inferior performance than dies on the main areas of the wafer. For example, a 300 mm wafer may produce 500 prime dies and a 200 mm wafer may produce 200 prime dies, now logistics is complicated even more to keep track of how many 200 mm wafers to how many 300 mm wafers in order to produce X number of final stacked pseudo 3D NAND packages. If both lines are 200 mm wafer or 300 mm wafer, then this complication would be dramatically reduced. That is not to say that YMTC was not creative. They were. But hardly 'groundbreaking'.
Already, I have at least %75 understanding of how YMTC did it. I would make a good ProcEng or TestEng for them.
That is a 26 yrs old SRAM 200 mm wafer atop some 64gb 300 mm NAND wafers. All of them are functionally dead. The NAND wafers were 'killed' by me personally for a special project that involved some important entities outside the normal customers list. Ain't that hard to make a fool out of you, little man.
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