Tsinghua Uni's XUANWU X01 Reconfigurable RRAM PUF chip 
Tsinghua Micro-Electronics Department Qian He and Wu Huaqiang team made important progress in the field of physical unclonable function chips
Tsinghua News Network, March 22nd, recently, the team of Professor Qian He and Professor Wu Huaqiang of the Micro-Nano Electronics Department at the 66th International Solid State Circuits Conference (ISSCC 2019) with "resistance memory-based with 6 × 10-6 raw bit errors The title of Reconfigurable RRAM PUF Utilizing Post-Process Randomness Source with <6×10-6 N-BER), reports the world's first resistive memory (RRAM) based physics The non-cloning function (PUF) chip design, the chip has a significant improvement in reliability and uniformity compared to the previous work, and has a unique reconfigurable ability to achieve efficient hardware security protection. The chip code name is XUANWU, which means "Xuanwu", one of the four ancient Chinese beasts with extraordinary defensive capabilities.
Physical unclonable function chip (XUANWU X01)
This work has received the attention of
Nature Electronics . On March 15th, in its latest publication, Research Highlights gave a key report, arguing that the ability to reconfigure a brand new PUF chip is a unique feature that greatly reduces key over-keying. Use and change the risk of hardware ownership. The article also pointed out: "Tsinghua University has developed a PUF chip based on resistive memory, which has passed the random test of the National Institute of Standards and Technology of the United States. Using the differential resistance method, the original bit error rate is low. At <6×10-6, the stability of the PUF chip against environmental changes was verified.”
With the widespread use of intelligent hardware and the increasing security threats in the semiconductor supply chain, hardware security has become more and more important, and software-only security protection has been unable to meet the demand. In recent years, physical unclonable functions have become a new means of hardware security protection. The integrated circuit PUF can exploit the inherent randomness of the device (such as the randomness of the process) to produce an unpredictable response under specific excitations, thereby acting as a hardware "fingerprint" that uniquely identifies the chip. However, the conventional integrated circuit PUF has two obvious disadvantages: First, there is a certain inherent paranoia in the deviation of the process, resulting in insufficient randomness of the PUF output. Secondly, since the process deviation is directly generated in the integrated circuit manufacturing process, once it is generated, it cannot be changed, and the output of the PUF cannot be reconstructed. In this case, when the PUF encounters multiple attacks or runs out of life, the PUF-protected hardware will again encounter hardware security threats.
As a new type of memory, RRAM uses the resistance value of the device to store information. Compared with traditional flash (flash) and dynamic random access memory (DRAM), RRAM has many advantages such as high speed, low power consumption and small area, and is one of the important candidates for a new generation of high performance memory. In addition, RRAM is widely used in brain-like computing because of its unique neuron-like properties. Since the working principle of RRAM is based on the fracture and growth of conductive filaments, this process has strong randomness, so that the resistance of RRAM exists between device-to-device (D2D) and the randomness between cycle and cycle (C2C). These random features also make it suitable for hardware security protection.
In view of the shortcomings of traditional integrated circuit PUF, taking advantage of RRAM, Pang Yachuan, a Ph.D. student at Tsinghua University's micro-nanoelectronics department, first introduced a reconfigurable physical unclonable function chip based on randomness of RRAM resistors on ISSCC2019. The report proposes a resistive differential method for generating PUF outputs to eliminate the inherent effects of process variations and voltage drops (IR drops). To implement this method at the circuit level, the team designed a high-precision sense amplifier circuit to accurately compare the resistance of two RRAM devices. A large amount of test data shows that the designed RRAM PUF has the lowest original bit error rate, the smallest unit area, the best uniformity and the unique reconfigurability compared with the previous work, which can effectively resist physical attacks. Very good development potential.
XUANWU X01 technical indicators
IEEE ISSCC（International Solid-State Circuits Conference 国际固态电路会议）始于1953年，是集成电路设计领域最高级别的学术会议，素有“集成电路领域的奥林匹克”之称。
清华大学微纳电子系博士生庞亚川为该论文的第一作者，吴华强教授为通讯作者。该研究得到了国家自然科学基金委、国家科技部、北京市科委、北京未来芯片技术高精尖创新中心等相关项目的支持。
团队合影（从左至右分别为钱鹤、庞亚川、吴华强、高滨）
近年来，微纳电子系钱鹤、吴华强团队围绕阻变存储器的关键科学问题，从材料器件优化、架构设计到系统集成、芯片应用等方面开展了系统研究，在国际期刊如《自然·通讯》《先进材料》《纳米快报》及领域顶级学术会议如国际电子器件会议（IEDM）、超大规模集成电路会议 （VLSI）、国际固态电路会议（ISSCC）等发表多篇学术论文，为阻变存储器芯片的产业化打下技术基础。
报道链接：
https://www.nature.com/articles/s41928-019-0227-0
http://news.tsinghua.edu.cn/publish...143543082222110/20190320143543082222110_.html
AiRiA's Watt A1 QNPU chip for edge computing
中科院AI团队将打造世界首款低比特量化神经处理芯片
3月21日，中国科学院自动化研究所南京人工智能芯片创新研究院（下简称“AiRiA研究院”）“普惠AI，芯向边缘”战略发布会在北京举行。会上，AiRiA研究院常务副院长程健透露，该团队自主设计的量化神经处理器（QNPU）即将于今年底流片，定名为“Watt A1”。在回应《中国科学报》提问时，程健表示，这将是世界上首款主打低比特量化技术的人工智能芯片。
In the on-site display page, the Watt A1 will use TSMC's 28nm process technology with a peak power of 24Tops (characterizing the number of integer operations per second, in teraflops per second), supporting 1080P four-way real-time monitoring, and frame efficiency. The ratio is up to 6Tops/W.
Like the AiRiA Institute's "core to edge" theme, Watt's positioning is the AI chip for edge computing. "Quantitative neural processor is very suitable for the edge, it can maintain high performance under the limited power consumption, cost, etc." Cheng Jian told the Chinese Journal of Science, the QNPU developed by the team can even be processed on-chip A very large-scale neural network, which avoids the "memory wall" problem that has attracted much attention in the field of chip computing.
"Memory Wall" refers to the performance of memory performance is not as good as the performance of the processor, and severely limits the performance of the processor. Cheng Jian told reporters: "Data calculations are processed on-chip. There is no need to access the external memory repeatedly. There is no problem with the 'memory wall', which can greatly reduce the power consumption of the chip itself and greatly improve the speed of reasoning."
As a result, Cheng Jian said that power consumption and cost are kept low, and computing power remains high. Therefore, QNPU is very suitable for edge computing for "low power, low latency" computing scenarios.
Lian Cong, deputy dean of the AiRiA Research Institute, added to the Journal of the Chinese Academy of Sciences that the quantitative technology is not unique to the AiRiA Institute, but achieving a quantization accuracy of 3 bits or less is an advantage that other teams have unmatched. Very good, but we can do 3 bits, 2 bits or even 1 bit."
With the prosperity of the Internet of Things and the imminence of 5G commercialization, edge computing has become more and more popular, and it is quite similar to central computing (cloud computing). Major computing vendors and cloud service providers are also facing the edge computing layout.
"We are the latecomers of the AI chip, but we combine our own advantages and choices to develop the best edge calculation direction. From here, on the one hand, we are based on our judgment on the market. On the one hand, we have more than 10 years of technical accumulation. Support our judgment." Cheng Jian said to the Journal of Chinese Academy of Sciences.
AiRiA Research Institute was established in September 2017 in Qilin High-tech Zone, Jiangning District, Nanjing. It relies on the Institute of Automation of the Chinese Academy of Sciences, focusing on the research and development and technology promotion of artificial intelligence and chip key technologies.
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