Open-source IC architecture taking off in China

[Nan Yang]

The law of unintended consequences, often cited but rarely defined, is that actions of people—and especially of government—always have effects that are unanticipated or unintended. ​

​

Open-source IC architecture taking off in China​

Government, academia and the private sector are all working together to avoid US sanctions

By SCOTT FOSTER
DECEMBER 6, 2022

China's chip industry has been hit by US sanctions. Image: WION

From consumer electronics to artificial intelligence, they are developing an independent Chinese semiconductor device eco-system, with the support of the worldwide open-source RISC-V community.

Proprietary instruction set architectures from Intel, AMD and other American companies are subject to direct US government control. Those from Arm, the hugely successful British RISC design company owned by Japan’s Softbank, are regarded by the Chinese as high risk due to potential US influence on their owner.

The RISC-V Foundation was established in Delaware in 2015 to support and manage the open-source technology, with the Institute of Computing Technologies of the Chinese Academy of Sciences as one of the founders. Others founding members include Google, Qualcomm, Western Digital, Hitachi and Samsung. Huawei and Alibaba joined the organization later.

In 2020, the Foundation was incorporated in Switzerland as the RISC-V International Association, moving out of the United States to avoid potential disruption caused by then-president Donald Trump’s anti-China trade policy. China was lucky that Trump, while inflicting severe punishment on Huawei and ZTE, did not target RISC-V, and that RISC-V moved to Switzerland before the more thorough and exacting Joe Biden administration took power.

RISC-V now claims more than 3,100 members in some 70 countries. Its mission statement reads: “RISC-V combines a modular technical approach with an open, royalty-free ISA – meaning that anyone, anywhere can benefit from the IP contributed and produced by RISC-V. As a non-profit, RISC-V does not maintain any commercial interest in products or services. As an open standard, anyone may leverage RISC-V as a building block in their open or proprietary solutions and services.”

Officials in Shanghai introduced financial incentives for RISC-V development in 2018. That same year, also in Shanghai, Chinese RISC-V specialist StarFive was founded with the support of SiFive, the technology leader headquartered in Santa Clara. Backed by Intel Capital and Qualcomm Ventures, SiFive promotes RISC-V worldwide.

StarFive’s RISC-V central processing units (CPUs) are designed to compete with Arm in computing, data center, telecom, auto and industrial applications. Fabricated using 12-nm process technology, they are aimed at high volume markets and are within the production capabilities of Chinese foundries should the Americans decide to shut off the company’s access to TSMC.

StarFive’s VisionFive 2 compact single-board computer sells for around $60 abd features a 1.5 GHz quad-core RISC-V processor, support for up to 8GB of RAM, and a GPU with 3D graphics support. Photo: Liliputing

StarFive also develops tailored RISC-V system-on-chip infrastructure solutions such as a city gas pipeline system that includes smart meters, data transmission, system management and data and network security. According to management, “StarFive has developed an industrial internet security product with completely independent intellectual property rights.”

StarFive’s other products include an image and video processing platform for home, public and industrial security.

In August of this year, T-Head, the IC design division of Alibaba, announced the Wujian 600 development platform for the design of system-on-chip devices for embedded applications in video conferencing, medical imaging, home-use robots and other products.

According to Calista Redmond, chief executive of RISC-V International, “The Wujian 600 development platform enables powerful edge SoCs with enhanced frequency and increased storage for robust edge-AI computing. The developer ecosystem supporting Xuantie [the CPU used in an advanced Wujian SoC] on Linux and Android further strengthens the RISC-V software ecosystem.”

Nuclei System Technology, also headquartered in Shanghai, was founded in 2018 by Bob Hu, the designer of the first open-source RISC-V core in China and an active promoter of RISC-V technology. The company’s products include processor IP for microcontrollers, edge computing, security, storage, virtual reality, data center, telecom and low power internet-of-things applications.

Among its partners, Nuclei lists the RISC-V Foundation (RISC-V International), the China RISC-V Alliance, the China RISC-V Industry Alliance (Shanghai-based RISC-V startups and IC design contractor VeriSilicon Holdings), the Shanghai IC Industry Association (SICA), four universities, Xiaomi, Tencent and numerous other Chinese companies.

Those companies include Geoforce Chip, a designer of power management, audio and communications devices; TIH Microelectronics, which specializes in cryptographic and network security chips; Taolink Technologies, which focuses on wireless IoT technology; and ChipIntelli, which provides speech recognition and data processing software and chip designs.

RISC-V technology has become increasingly popular in China. A RISC-V Shanghai Day in 2018 attracted fewer than 1,000 attendees. The first RISC-V Summit China, hosted by ShanghaiTech University and the Chinese Academy of Sciences’ Institute of Software in 2021, attracted more than 30,000 attendees, most of them online due to Covid. The second, held in August of this year, reportedly attracted more than three times as many.

The RISC-V Summit China 2022 included keynote speeches by Mark Himelstein, the CTO of RISC-V International, and Yungang Bao, the leader of the XiangShan high-performance RISC-V processor development team at the Institute of Computing Technology, Chinese Academy of Sciences, and more than 80 tutorials and technical presentations. Sponsors included Alibaba’s T-Head, Nuclei System Technology, Qinheng Microelecronics, and Andes Technology from Taiwan.

Last April, the Institute of Computing Technology announced that the new Beijing Open Source Chip Research Institute had started operations with projects based on the XiangShan processor. XiangShan is a joint creation of the Chinese Academy of Sciences; the Pengcheng Laboratory in Beijing, which is dedicated to telecom and internet-related R&D; Vcore, a RISC-V processor designer; and private companies including Alibaba and Tencent.

There has been an explosion of RISC-V-related activity over the past several years that seems likely to continue into the foreseeable future. In short, US sanctions are causing what they were intended to prevent – the development of an independent Chinese IC product portfolio that will both reduce China’s dependence on imported technology and support its domestic and export industries.

This has been accomplished with the support of the worldwide open-source RISC-V community. As noted on the RISC-V International website, “RISC-V does not take a political position on behalf of any geography. We are proud to see organizations from around the world working together in this new era of processor innovation.”

Follow this writer on Twitter @ScottFo83517667.

 

[kankan326]

China has decided to get rid of US control on IC industry from the very root.

 

[firohot4321]

Can this architecture be the basis of advance ai chips

 

[Dungeness]

Chinese did it before, that is why they have China Space Station and Beidou Navigation system now, and they can do it again.

 

[Chat SAMOSA]

Everything is open source to CCP. It's a just a matter of access.

 

[Dungeness]

Everything is open source to CCP. It's a just a matter of access.

If you have to bad mouth China, at least come up with something more original.

 

[Chat SAMOSA]

If you have to bad mouth China, at least come up with something more original.

I don't have to or want to bad mouth China. It is a truly great country - not kidding or satire. It has made fantastic contributions to humanity. Why would I bad mouth China ?

 

[Dungeness]

I don't have to or want to bad mouth China. It is a truly great country - not kidding or satire. It has made fantastic contributions to humanity. Why would I bad mouth China ?

You guys just can't handle the reality that India is just a piece of sxxt in front of China, so your lot just have to vent your frustration on anything Chinese. I said this with a lot of respect for ancient Tianzhu (there was no India back then) culture. Loser!

 

[Chat SAMOSA]

You guys just can't handle the reality that India is just a piece of sxxt in front of China, so your lot just have to vent your frustration on anything Chinese. I said this with a lot of respect for ancient Tianzhu (there was no India back then) culture. Loser!

Huh? So you don't think China is a great country ? Fine with me.

Bad mouthing India as you did doesn't reflect on India but just on you as a frustrated individual. Get better.

 

[Ali_Baba]

China has a large enough population, and economy that it can make a success of making the transition from X86/ARM instruction sets to RISC-V as it has enough control to create critical mass of infrastructure and the associated software ecosystem that needs to support the instruction set. The two are tied together and required to make it a success. It is not just a "hardware problem", but software too..

Linux is Opensource aswell - so you can for your core workflows as a country - live outside the American ecosystem if you need to.

Russia tried to do this - but it does not have a large enough economy, industrial base, population or R&D capabilities to make it happen and that is why it is forced to scavenge CPU's from washing machines to put them inside its cruise missiles ....

 

[Beidou2020]

Best thing to happen for the development of China’s semiconductor industry are these sanctions. It has united all of Chinese society towards the goal of semiconductor independence. Americans will look back at this in a few years as a great strategic error to unite all Chinese society behind one common goal.

 

[kankan326]

Best thing to happen for the development of China’s semiconductor industry are these sanctions. It has united all of Chinese society towards the goal of semiconductor independence. Americans will look back at this in a few years as a great strategic error to unite all Chinese society behind one common goal.

It's not a strategic error. Without semi-conductor bans, Huawei would surpass Apple in several years. By then Huawei would be a company that is equal to Apple+Qualcomm+part of Google(in AI & OS) + Ericsson. Let alone there are many other very competitive Chinese high tech companies. You can't imagine how bad US economy would be if it loses Apple and how powerful China's high tech would be if US didn't issue the bans.

 

[Nan Yang]

Examining the Top Five Fallacies About RISC-V

By David Patterson 12.13.2022

In a little over a decade, RISC-V has arguably become at least the third most important instruction set architecture (ISA) for future applications of computing. In the next few years, it may become just as surprising to pick a proprietary ISA over the open RISC-V for a new project as it would be to pick a closed alternative to Ethernet or USB.

My colleagues at UC Berkeley and I predict that by the end of this decade, the dominant ISA for future product development will be the open RISC-V architecture. Companies around the world are already designing with RISC-V and the momentum is rapidly increasing, so this is a good time for the industry to take a closer look at RISC-V and examine some fallacies about it.

Fallacy No. 1: RISC-V is an open-source processor, like Linux is an open-source operating system.​

Linux has a single-master open-source code base you can download, while RISC-V is an open specification of the hardware/software interface, for which there are many different implementations. A better analogy than Linux is Ethernet, as both Ethernet and RISC-V are free and open specifications.

Before the Ethernet standard, companies had their own proprietary local area networks. In 1980, Digital Equipment Corporation, Intel, and Xerox (DIX) joined forces to create a local network standard based on Ethernet. They also created an organization — IEEE 802.3 working group — that has advanced the Ethernet standard over the past four decades. Ethernet made rapid advances in cost and performance because many companies could build network products that ran the same software stack on top of the Ethernet standard.

The popular Universal Serial Bus (USB) also followed the Ethernet game plan by providing a free and open standard for peripheral interconnect that is embraced by many companies plus an organization to evolve it.

Like Ethernet and USB, RISC-V is an open standard (which is also run by a foundation) that lets many organizations design hardware, which fosters competition to improve its cost performance and develop a rich, shared software ecosystem that offers RISC-V products in many markets. Like Ethernet and USB, you can buy RISC-V hardware, build it yourself, license designs, or download open-source designs.

Fallacy No. 2: Picking an established, closed ISA is a safer business decision than picking the open RISC-V.​

It’s easy to forget that a closed ISA is tied to the success of the company that owns it, and it can disappear if the company falters. For example, the once-popular DEC VAX, DEC Alpha, and Sun SPARC ISAs are extinct.

It’s also hard to remember that closed ISAs are intellectual property that can be sold to companies with different goals than its predecessors. For example, the MIPS ISA has had more than a half-dozen owners, and so far, the Arm ISA has had three: Acorn, ARM Holdings plc, and Softbank. By comparison, RISC-V is driven by the collective participation of hundreds of companies in a neutral open-standard organization, RISC-V International. Their collective interests determine the evolution of RISC-V through this nonprofit foundation.

Like Ethernet and USB, RISC-V is not tied to the fortunes of any one company, so it is a more prudent bet for a company’s software ecosystem development for the long haul.

Fallacy No. 3: Closed ISAs do not have fragmented software ecosystems.​

Older closed ISAs have suffered from unforeseen incompatibilities over their long lifetimes. Examples include:

• Despite trying to share the x86-64 ISA, AMD and Intel require different virtual machines.
• Intel AVX-512 is significantly fragmented (e.g., the ML floating-point format BF16 comes and goes).
• ARMv1 through ARMv7 use a 32-bit address space but are incompatible with ARMv8-A and successors, which offer both 32- and 64-bit address versions. ARMv8-M adds new features to the older 32-bit ISA but is incompatible with ARMv8-A.

No software environment is more fragmented than today’s system-on-chip (SoC) for edge devices. They include many incompatible ISAs and software stacks for the many types and brands of processors (application CPUs, embedded CPUs, DSPs, ML accelerators, and ISPs). One reason is because these processors use closed ISAs that cannot be used for third-party IP, so each processor block has its own ISA.

Fallacy No. 4: RISC-V’s modularity leads to a more fragmented software ecosystem than those of closed ISAs.​

This fallacy has been raised since my colleagues and I began advocating for RISC-V, so it’s not been neglected. Some market segments require a stable ISA and even binary compatibility, which RISC-V addresses with profiles. They specify a set of ISA choices from the standard extensions that capture the most value for most users in a market, enabling the software community to focus resources on building an appropriate software ecosystem. Similarly, hardware vendors structure their offerings around standard profiles to ensure their designs will have mainstream software support. For example, RISC-V offers them for 64-bit address UNIX systems. Profiles are the foundation upon which portable apps and OSes can be built.

Beyond profiles, the RISC-V ISA offers the exciting possibility of a common base ISA with custom enhancements and a shared software stack across the many processors of an SoC. RISC-V potentially could dramatically reduce the fragmentation of today’s SoC software ecosystems.

Fallacy No. 5: Given the points above, RISC-V cannot become the dominant ISA.​

As long as there are both 32-bit and 64-bit address versions, there is no technical disagreement that a single base ISA could be used everywhere from embedded systems to supercomputers; the main argument is a business one, of whether it should be a closed ISA or an open ISA. If we do achieve a lingua franca for computing, it seems self-evident that it would be too dangerous for the fate of the entire information technology industry to be tied to the fortunes of a single company. It would be much safer if we could instead depend upon a free and open standard, just as we did for networking and peripheral interconnect.

 

[fitpOsitive]

@jamahir

But the question is, who will take the responsibility of the reliability of the tools?

 

[jamahir]

This has been accomplished with the support of the worldwide open-source RISC-V community. As noted on the RISC-V International website, “RISC-V does not take a political position on behalf of any geography. We are proud to see organizations from around the world working together in this new era of processor innovation.”

That is quite nice.

Can this architecture be the basis of advance ai chips

I don't know about the entire range of different implementations of RISC-V around the world but SiFive, the American company mentioned in the OP, has developed a vector processor implementation which can be used in AI :

RISC-V Vector Processing is Taking Off | SiFive​

By RISC-V Community News June 20, 2022 No Comments

The RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector processing across a wide spectrum of applications since vectors promise to solve multiple current industry design and development challenges. Licensable IP is already commercially available today and more solutions are expected in the marketplace soon as the robust RISC-V ecosystem embraces the advantages of RISC-V vector solutions.

So why the shift to vector, which was once mainly reserved for the world’s most powerful supercomputers? Today’s data driven applications increasingly require multiple cores combined in ways that can create complex and inefficient environments. When you add in capabilities like artificial intelligence, machine learning, or computer vision you introduce additional challenges like managing power consumption, extra data movement, the need for multiple libraries, and issues with generational incompatibility.

Importantly, RISC-V provides a trusted, standard foundation and is supported by a robust, growing ecosystem. This offers the designer tremendous flexibility. To make vector effective it needs to be delivered in an easy-to-program, more efficient environment. RISC-V has tremendous benefits here.
The RISC-V Vector ISA is a very clean and optimized set of instructions, with the base ISA numbering around just 300 instructions, far smaller than a typical packed-SIMD alternative. Crucially these powerful instructions can each do a lot of work. Denser code means more efficient use of the instruction cache, leading to significantly more power efficient computing. Packed-SIMD and GPU implementations can lead to multiple new instructions being required and as a result chip size increases, (as new data types are introduced) and also additional code required to accommodate “corner case” handling, increased code size and resulting bill of materials cost increases as well as greater power consumption.
RISC-V vectors are a powerful and super efficient (in code size, performance, and area) alternative to the inefficient use of packed-SIMD and GPUs for the processing of large datasets. The ISA is efficient and scalable to all reasonable design points. This means it’s equally ideal from low-cost designs to the highest performance applications. To provide this flexibility the ISA needs to be able to support in-order, decoupled, or out-of-order microarchitectures, along with integer, fixed-point and/or floating point data types.

The ability to utilize different vector lengths with the same software code offers scalability and flexibility. Another big advantage is the reduced software complexity. By eliminating the need for multiple accelerators or DSPs users can achieve significant power reductions and much greater efficiency, which is a big focus across every segment today.

A key defining features of the RISC-V Vector ISA is that it is vector length agnostic. Software code that has been written for any RISC-V vector compliant processor will work on any other RISC-V vector processor. This is valuable to the customer from a software reuse perspective.

Imagine a first-generation end-product was designed around a 256-bit length vector register processor, taking advantage of the balance of power, performance, and area for that first design but then, with market success, new requirements evolved for a second generation product that required a longer vector register length processor with 512-bit length vector registers. With RISC-V not only will the software code execute directly the updated system, but the code performance will improve immensely, without having to change even one line of code. For the customer this offers greatly reduced design and development time, and speeds time-to-market for the second-generation product.

RISC-V vector solutions enable the creation of a unified, efficient, and easy to program design, allowing designers to add differentiation to their product to better target demanding and rapidly changing market requirements. As an open standard, much of the code written for RISC-V vectors will be available in the open standard domain. This allows developers to access the large and growing ecosystem of RISC-V based algorithms, along with access to a full range of open standard and commercial grade tools for compilation, modelling, debug and trace. For the developer this access to open source algorithms provides a standardized and stable approach to algorithm development, and reduces time and development costs.

Applications today are being looked at across a wide spectrum from products like security cameras, where AI comes together with a need for low battery consumption, to hyperscale applications, aerospace and automotive. The opportunities are virtually endless,
For those interested in finding out more about the background and history of the RISC-V ISA, there is an introductory video available here, described by one of the inventors, Andrew Waterman. SiFive, which with its SiFive® Intelligence™ X280 and SiFive Performance™ P270 Processors has products available today, has also posted some tutorials and other material to help educate those wanting to understand more about vector solutions here.

It is an exciting time for RISC-V and the momentum will only accelerate further as the ecosystem continues to expand rapidly and awareness of the many benefits of RISC-V vector solutions spreads.

Another approach can be combining RISC-V implementations, whether vector as above or its opposite - scalar, with an electronic analog processor in manner similar to that done by the American company Mythic.

Russia tried to do this - but it does not have a large enough economy, industrial base, population or R&D capabilities to make it happen

Tried to do what ? Modern Russia has its own processor architecture called Elbrus which has an instruction set that is self-developed but closed source but it also includes a run-time software translator for the Intel x86 and Intel x86-64 instruction sets so that the processor can run the regular Linux and Windows OSes. The Elbrus processor sits within a regular PC system board and depending on the variation is meant for servers or regular PCs :

Supported operating systems​

The Elbrus-8S and -SV processors support binary compatibility with Intel x86 and x86-64 processors via runtime binary translation. The documentation suggests that the processors can run Windows XP and Windows 7. The processors can also run a Linux kernel based OS compiled for Elbrus.

and that is why it is forced to scavenge CPU's from washing machines to put them inside its cruise missiles ....

If that is true what is the problem ? NATO's Al Qaeda and "Muslim" Brotherhood boys in Syria were scavenging metal factories to produce extra-armor for vehicles and you would have been championing that.

@jamahir

But the question is, who will take the responsibility of the reliability of the tools?

What kind of tools are you talking about ? The regular software compilers for RISC-V or alternatives to Xilinx Vivado and EDA ? Because I think the former category is available in the GNU community.