F-22Raptor
ELITE MEMBER
- Joined
- Jun 19, 2014
- Messages
- 16,980
- Reaction score
- 3
- Country
- Location
Taiwan Semiconductor Manufacturing Company (TSM) recently revealed the much-awaited initial specifications for its 3nm (N3) process. Given that TSM's 3nm was already rumored to not launch on a two-year cadence, as opposed to its most recent ramps, as well as just being such a small number, one might have excepted a groundbreaking node, such as a move to next-generation gate-all-around transistor technology and a 2x transistor density scaling.
Instead, TSM revealed a lackluster 1.7x scaling while remaining on the regular FinFET technology. In terms of density scaling, this is almost as slow of a pace as Intel's 10nm and noticeably worse than its N5 node, which has 1.84x scaling and, being in production now, is following exactly two years after N7.
TSM inherited its current process leadership from Intel (INTC) due to the latter's historic 3-year delay of 10nm. Any surprises aside, given this new information, TSM's process leadership seems done, as Intel is ready to at least achieve parity at 7nm.
Background
For some essential background, process names have become marketing names, and do not refer to any physical feature size of the technology, as has been the case for over two decades now. The building blocks of a process node, transistors, contain multiple features, materials, and sizes and can't be described by one number.
In general, the name has become an overstatement of the actual smallness of transistors. For reference, atoms are about 0.2nm, so this suggests that TMS's 3nm would be almost as small as possible. While, obviously yes, transistors have become minuscule, even at 3nm many pitches between transistors are still expected to be actually over 16-20nm in length. There's still plenty of room at the bottom and the roadmaps of those companies are full. As I will detail below, moving to gate-all-around (GAA) will yield some further opportunities to improve density without having to shrink features, by exploiting 3D stacking.
Secondly, for these technologies, EUV patterning is critical to achieving those small feature sizes (possible because of its much smaller wavelength). TSM's 5nm is the first very high volume node to use EUV in a substantial amount of layers (10-20), and 3nm should use it even more.
The next improvement in litho after EUV will be 'high-NA' litho. The 0.55NA number vs. the current 0.33NA implies it is even bigger than the current EUR 130 million tool. However, the introduction of this tool is expected around 2023, likely after the 3nm timeline. Given the "call to action" in the below quote, it seems Intel is intent on using it for its 5nm node, in production in 2023. According to SemiEngineering:
So, it's imperative to develop high-NA. "In parallel with continued improvements to 0.33, we need to develop 0.55," said Mark Phillips, an Intel fellow and director of lithography hardware and solutions at the chip giant, in a recent presentation. "Intel has a robust roadmap of process nodes that requires the resolution and EPE (edge placement error) benefits of continued EUV lithography development. High-NA EUV is needed to avoid 0.33 NA mask splits, eliminates the cumulative EPE for mask splits, reduces process complexity and lowers cost. We need the ecosystem to be ready to support it by 2023."
Speaking to lithographers and mask makers at the event, Philips' presentation was a call to action to keep high-NA EUV on track and address the gaps with the technology, namely masks and resists. High-NA always has been targeted for 2023, but there is a danger that it could slip based on past events. Current EUV was several years late before moving into production.
The Technology
As WikiChip reports, TSM disclosed that its N3 will feature a 1.7x density improvement compared to N5, which just entered production. TSM says N3 will provide 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed; quite standard claims for a new process.
N3 status:
More plausibly, it could also indicate that the FinFET is running out of steam. As SemiEngineering already scooped a while ago, TSM's N3 is expected to extend the FinFET technology, which Intel introduced in manufacturing in late 2011 with 22nm and TSM in early 2015 at N16. It is unclear why TSM has not opted to transition to its natural successor yet, the gate-all-around also called nanowire or nanosheet.
In basic terms, a GAA covers all four sides of the transistors, while a FinFET only covers three sides, and a traditional planar one only one side. This gives it better current control, leading to improved switching characteristics. Although, as it is more of an evolution, the change is not expected to be as large as the move to FinFET. Nevertheless, the FinFET was always forecasted to run out of steam somewhere at the single digit nodes, and the GAA comes with some further characteristics that will enable it to continue Moore's Law.
Specifically, the GAA allows for 3D (vertical) stacking of the nanowires/nanosheets (the GAA equivalent of the fins). In FinFETs, multiple fins are used per transistor to increase drive current (performance). This, of course, makes the transistor cell larger than one with just one fin per transistor would be. As the wires/sheets can be stacked in GAA, this provides an additional way to scale density, besides just shrink the feature sizes. Moreover, this method might also be extended to stacking the NMOS and PMOS transistors - which together form a standard CMOS. This is called a Complementary FET or CFET.
As a numeric example, it should be clear that moving from a CMOS FinFET with 3 fins per transistor to a stacked nanowire CFET, theoretically, yields up to a 6x improvement in density without any further changes in feature size - which should also be possible due to the GAA's better characteristics as described.
Samsung (OTC:SSNLF) will move to this, as the first foundry as it has been marketing for a few years now, at its own 3nm in 2022. Samsung's 3nm is expected to be quite close to TSM's N5 in terms of density; however, since it is Samsung's first real shrink after its 7nm - its 5nm is a 7nm derivative. Intel is expected to make the move at its 5nm in late 2023, per its roadmap.
This means TSM will be last to transition to the post-FinFET era in leading-edge semiconductors. Without knowing any details, some might interpret that TSM is simply extending a proven FinFET ecosystem to its limits, but from a purely technological perspective, on the other hand, it could foreshadow that TSM will be falling behind, as others will likely be transitioning to second-generation GAA by the time TSM ramps its first generation. As this is difficult to evaluate, I will focus on the density aspect.
The Cadence
Most interesting about N3 is its cadence, which had previously been hinted at via the timeline of its 3nm fab construction.
Not only is it just a 1.7x shrink while remaining a FinFET, but it also is not on TSM's two-year or less cadence it has followed since the introduction of 20nm in late 2014. While it is slated for risk production in 2021, two years after N5's 2019 risk production start in numbers, the volume production was given more precisely and is targeted for the secondhalf of 2022. This implies N3 might not hit the shelves until 2023, likely N3-based phones launching towards the end of the first quarter or early second quarter of 2023, and missing the 2022 iPhone cycle.
This 2.5-year cadence with subpar density improvement gives time for competitors to catch up.
And if they achieve in following their roadmaps, they will. Intel's over 3-year 10nm delay, which gave TSM the opportunity to take the process lead, was partly 'made up for' by virtue of 10nm being a 1.5 node shrink in density. Perhaps, then, the most interesting figure about TSM's N3 is that its pace of improvement (1.7x/2.5yrs) is almost as slow, mathematically, as Intel's 10nm (2.7x/5.0yrs), as 1.7 squared equals 2.9, just a bit higher than Intel's 2.7.
This results in following numbers of density improvement CAGR (annual rate):
Of course, all discussion below assumes no delays from either side.
Given that Intel will move to GAA/nanowire at 5nm, this already suggests that its 7nm might not be a bad point of comparison for TSM's N3. And indeed, based on the data we currently have, I project TSM's N3 will be just a little bit better than Intel's 7nm.
However, Intel's 7nm scaling factor seems a bit ambiguous, or contradictory, based on different statements by Intel management it might be 2.0x, so I will interweave a bit of discussion about this. Of course, people will pick the number that suits them best in the absence of final data.
Anyhow, following quote from then-CEO BK in the Q1'18 call makes it clear that 7nm will scale by 2.4x:
As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in [the 10nm] case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.
As Intel discussed at length in its 2017 Technology and Manufacturing Day, 10nm achieved a 2.7x scaling, which Intel called hyperscaling. Intel also introduced a clear, standard density metric, which should make comparisons across the industry possible. As it revealed, according to this metric, 10nm achieved a 100MTr/mm2 density - 100 million transistors per square millimeter. A 2.4x scaling, then, makes for a density of 240MTr/mm2.
The graph below shows WikiChip's numbers for TSM:
This confirms my statement that TSM N3 will be very close to Intel 7nm - N3 has just a 21% higher density. This results in following comparison:
Just a few quarters later, at the end of 2023, Intel will move to its 5nm node with a 2x improvement in density.
The graph above shows the extremely long period Intel remained at 14nm, which allowed TSM to leapfrog Intel with the introduction of its own N10 and N7. Intel achieved parity, or a slight edge, with TSM midway TSM's N7 cycle (where we are now), although Intel's 10nm is still quite limited in volume. TSM is charging ahead to 5N later this year but will stay there for a more prolonged time, allowing this time Intel to leapfrog TSM with 7nm and 5nm shortly after 3N.
This means from 7nm onward, Intel will take the process lead back and have the most dense process for the majority after that period; TSM will only have the lead for a few quarters in 2023, by a small margin. This means TSM's four-year process leadership that started in H2'17 will end in H2'21.
However, as I said, there has been some discussion about the exact scaling factor of Intel's 7nm. Some newer information suggests it might be 2.0x. Of course, since BK probably didn't just invent the 2.4x number out of thin air, this implies Intel might have reduced its 7nm targets to this alleged 2.0x factor. Intel, currently, has not provided any guidance as to when it will reveal the details of its 7nm node.
The 2.0x factor would be supported by following information:
• A slide from its 2019 investor meeting said 7nm would feature a 2x scaling factor. This could obviously be explained as only providing one significant digit, as rounding 2.4x would also result in 2x.
• Murthy, December 10, 2019, UBS Global TMT Conference:
So as we've said in the past, we've, we've moved more to a scaling factor around two X between 10 and 7." Again, Murthy is quite vague here with "around 2x".
• Bob Swan, December 3, 2019, Credit Suisse Technology Conference:
Now, the 22 to 14 was not a two times density. It was 2.4, um, the four and it was bumpy along the way, but it worked. And that working gave us the confidence that for 14 to 10, why don't we take the scaling factor up to 2.7. When you do that, the of trying to get more and more density or more and more performance, it's inside the fab. You need more and more revolution in each step inside the fab to deliver that kind of density improvement. (…) So along the way, we, uh, based on our confidence of past performance, we set a higher bar and it didn't work effectively, just took too long. Now good news is we feel like we've got fairly well dialed in. The bad news is it took too long. (…) The criteria is gotta be a more effective balance because customers want products every year. So more effective balances of great performance, but reliable and predictable delivery of new products in an annual, in an annual cadence. (…) Secondly, we're not going to try to do 2.4 scaling or 2.7 scaling. As we think about seven nanometer, you know, we put 2.0 back in line with historical trends as we think about fivenanometer which would be our competitors three nanometers. It's more like 2.0 we're thinking about. So we're not putting as much a challenge on the fab and not taken on so much complexity and design rules, which the more there are, the more complicated, the more complicated it is. So we're capturing these learnings from the past and applying them going forward.
Despite Intel saying in 2018 that 7nm would be a 2.4x scaling, in 2019, apparently, this was reduced to a 2.0x scaling factor, although Murthy, who is responsible for process development among other groups, a week later said it was "around 2x".
In any case, at the lower end of this 2.0-2.4x range, this means 7nm would be a 200MTr/mm2 node. This would give 3nm a more comfortable 50% density uplift but still over a year later. Intel's 5nm with, according to Bob Swan, again a ~2.0x scaling (400MTr/mm2) would follow within a year at the end of 2023 with, in its turn, a noticeable 38% density uplift over TSM N3.
Since ~40% is basically one year of Moore's Law, but Intel would follow within about three quarters, this would give Intel a slight (theoretical) process lead. Practically though, TSM and Intel would be on the same density curve (of initial process introduction, as different companies and kind of chips move to the leading edge at a different pace) but just with different introduction dates. As Intel said, it will have effectively achieved parity at 7nm.
Nevertheless, the pace of improvement seems firmly in Intel's favor, as TSM is on a cadence of at least two years while improving by about 1.7x to 1.9x per generation, while Intel is on a two-year cadence with at least a 2.0x improvement. This would hence give the definite process leadership back to Intel by 5nm: TSM's N2 might be ~520MTr/mm2 in the first half of 2025 compared to Intel's 5nm in late 2023, which would be around 400-480MTr/mm2. (A similar outcome to the scenario I described with the 2.4x scaling factor but just a node later in time.)
Even with this revised information, while Bob Swan compared its 7nm to TSM's N5 and its 5nm to TSM's N3, my analysis shows that Intel might be giving TSM a bit too much credit here, as TSM's N3/N2respectively clearly bear more resemblance to Intel's 7nm/5nm(respectively FinFET/GAA).
Intel, both its CEO Bob Swan and CFO George Davis, also publicly stated Intel is aiming to regain process leadership by 5nm, which my analysis confirms would be the case. (While not in time to market, if Bob Swan compares its 5nm to TSM N3, definitely in terms of density.)
In general, the landscape will become much more close/competitive than in the H2'17 to H2'21 time period. For example, Intel's 10nm is still in limited volume despite having theoretical parity at this moment on the curve (20Q2), but Intel said its whole portfolio will move to 7nm in 2022.
Risks
TSM said it has many options in development for N3. As SemiEngineering suggested, TSM could move to nanowire/GAA either at a later stage of N3 or at N2. If TSM, for example, introduces a GAA version of N3 in early 2024, then it won't lag behind Intel's 5nm too much. Of course, this is just speculation for now, but in the 2022 to 2024 timeline, Intel is currently on track to be the leader.
This article is also under the assumption that the companies deliver on their officially stated timelines/roadmaps. For TSM, this means volume production of FinFET N3 in the second half of 2022, which follows N5 which entered volume production in April. For Intel, this means launching the first 7nm product in late 2021 with 2.0-2.4x the density of 10nm, followed by the first 5nm GAA product in late 2023 with ~2.0x the density.
Under that assumption, Intel 10nm is, currently, by a thin margin the most dense process node available. TSM will comfortably take the lead with N5 later this year. Intel will take over the lead with 7nm in late 2021, although by less of a margin than N5 on 10nm. TSM's N3 should be the densest process in early 2023 and 5nm will take over in late 2023.
As one small detail, being a customer of TSM means that Intel should have pretty much as much insight into TSM's next-gen processes as its other customers should have. This could give Intel a slight advantage to know where TSM is heading and more visibility when it is making statements such as recapturing process leadership.
Takeaway
Moore's Law remains of utmost importance at the leading edge of semiconductor chips, as it determines so much of the final product.
The main point here is that TSM's 1.7x scaling target for N3 combined with a 2.5-year cadence implies an annual scaling rate that is almost as poor as what Intel's 10nm achieved inclusive of its delays. This means, for one, that N3 will miss the 2022 Apple (AAPL) iPhone cycle. TSM also retains the FinFET.
As I described, this will let Intel catch up.
Intel, meanwhile, said it is moving back to 2-2.5 year cadence. If Intel's 7nm maintains the 2.4x scaling factor BK described in 2018, then TSM's N3 will be basically a competitor of Intel's 7nm, with a slightly higher density, but Intel's 7nm will launch at least a year earlier.
The picture looks better if Intel's 7nm was dialed down to a 2.0x scaling factor: both companies would be pretty much on the same scaling curve, and hence the leadership crown might change hands a few times.
Still, Intel seems to have a higher pace of improvement: Intel's 5nm will launch a few quarters later, moving to nanowires/GAA and a density that is much higher than N3. Assuming no delays from either side.
TSM benefited hugely from Intel's historic 10nm delay, and N5 just entered production at least a year before Intel's 7nm, but its process leadership days seem numbered.
https://seekingalpha.com/article/43...ng-company-losing-process-leadership-to-intel
Instead, TSM revealed a lackluster 1.7x scaling while remaining on the regular FinFET technology. In terms of density scaling, this is almost as slow of a pace as Intel's 10nm and noticeably worse than its N5 node, which has 1.84x scaling and, being in production now, is following exactly two years after N7.
TSM inherited its current process leadership from Intel (INTC) due to the latter's historic 3-year delay of 10nm. Any surprises aside, given this new information, TSM's process leadership seems done, as Intel is ready to at least achieve parity at 7nm.
Background
For some essential background, process names have become marketing names, and do not refer to any physical feature size of the technology, as has been the case for over two decades now. The building blocks of a process node, transistors, contain multiple features, materials, and sizes and can't be described by one number.
In general, the name has become an overstatement of the actual smallness of transistors. For reference, atoms are about 0.2nm, so this suggests that TMS's 3nm would be almost as small as possible. While, obviously yes, transistors have become minuscule, even at 3nm many pitches between transistors are still expected to be actually over 16-20nm in length. There's still plenty of room at the bottom and the roadmaps of those companies are full. As I will detail below, moving to gate-all-around (GAA) will yield some further opportunities to improve density without having to shrink features, by exploiting 3D stacking.
Secondly, for these technologies, EUV patterning is critical to achieving those small feature sizes (possible because of its much smaller wavelength). TSM's 5nm is the first very high volume node to use EUV in a substantial amount of layers (10-20), and 3nm should use it even more.
The next improvement in litho after EUV will be 'high-NA' litho. The 0.55NA number vs. the current 0.33NA implies it is even bigger than the current EUR 130 million tool. However, the introduction of this tool is expected around 2023, likely after the 3nm timeline. Given the "call to action" in the below quote, it seems Intel is intent on using it for its 5nm node, in production in 2023. According to SemiEngineering:
So, it's imperative to develop high-NA. "In parallel with continued improvements to 0.33, we need to develop 0.55," said Mark Phillips, an Intel fellow and director of lithography hardware and solutions at the chip giant, in a recent presentation. "Intel has a robust roadmap of process nodes that requires the resolution and EPE (edge placement error) benefits of continued EUV lithography development. High-NA EUV is needed to avoid 0.33 NA mask splits, eliminates the cumulative EPE for mask splits, reduces process complexity and lowers cost. We need the ecosystem to be ready to support it by 2023."
Speaking to lithographers and mask makers at the event, Philips' presentation was a call to action to keep high-NA EUV on track and address the gaps with the technology, namely masks and resists. High-NA always has been targeted for 2023, but there is a danger that it could slip based on past events. Current EUV was several years late before moving into production.
The Technology
As WikiChip reports, TSM disclosed that its N3 will feature a 1.7x density improvement compared to N5, which just entered production. TSM says N3 will provide 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed; quite standard claims for a new process.
N3 status:
- many technology options in development
- decision based on maturity, performance, and cost
- full node scaling benefit in terms of PPA (performance, power, and density)
- more details at Technology Symposium on April 29th
- risk production scheduled for 2021 followed by volume production in the second half of 2022
More plausibly, it could also indicate that the FinFET is running out of steam. As SemiEngineering already scooped a while ago, TSM's N3 is expected to extend the FinFET technology, which Intel introduced in manufacturing in late 2011 with 22nm and TSM in early 2015 at N16. It is unclear why TSM has not opted to transition to its natural successor yet, the gate-all-around also called nanowire or nanosheet.
In basic terms, a GAA covers all four sides of the transistors, while a FinFET only covers three sides, and a traditional planar one only one side. This gives it better current control, leading to improved switching characteristics. Although, as it is more of an evolution, the change is not expected to be as large as the move to FinFET. Nevertheless, the FinFET was always forecasted to run out of steam somewhere at the single digit nodes, and the GAA comes with some further characteristics that will enable it to continue Moore's Law.
Specifically, the GAA allows for 3D (vertical) stacking of the nanowires/nanosheets (the GAA equivalent of the fins). In FinFETs, multiple fins are used per transistor to increase drive current (performance). This, of course, makes the transistor cell larger than one with just one fin per transistor would be. As the wires/sheets can be stacked in GAA, this provides an additional way to scale density, besides just shrink the feature sizes. Moreover, this method might also be extended to stacking the NMOS and PMOS transistors - which together form a standard CMOS. This is called a Complementary FET or CFET.
As a numeric example, it should be clear that moving from a CMOS FinFET with 3 fins per transistor to a stacked nanowire CFET, theoretically, yields up to a 6x improvement in density without any further changes in feature size - which should also be possible due to the GAA's better characteristics as described.
Samsung (OTC:SSNLF) will move to this, as the first foundry as it has been marketing for a few years now, at its own 3nm in 2022. Samsung's 3nm is expected to be quite close to TSM's N5 in terms of density; however, since it is Samsung's first real shrink after its 7nm - its 5nm is a 7nm derivative. Intel is expected to make the move at its 5nm in late 2023, per its roadmap.
This means TSM will be last to transition to the post-FinFET era in leading-edge semiconductors. Without knowing any details, some might interpret that TSM is simply extending a proven FinFET ecosystem to its limits, but from a purely technological perspective, on the other hand, it could foreshadow that TSM will be falling behind, as others will likely be transitioning to second-generation GAA by the time TSM ramps its first generation. As this is difficult to evaluate, I will focus on the density aspect.
The Cadence
Most interesting about N3 is its cadence, which had previously been hinted at via the timeline of its 3nm fab construction.
Not only is it just a 1.7x shrink while remaining a FinFET, but it also is not on TSM's two-year or less cadence it has followed since the introduction of 20nm in late 2014. While it is slated for risk production in 2021, two years after N5's 2019 risk production start in numbers, the volume production was given more precisely and is targeted for the secondhalf of 2022. This implies N3 might not hit the shelves until 2023, likely N3-based phones launching towards the end of the first quarter or early second quarter of 2023, and missing the 2022 iPhone cycle.
This 2.5-year cadence with subpar density improvement gives time for competitors to catch up.
And if they achieve in following their roadmaps, they will. Intel's over 3-year 10nm delay, which gave TSM the opportunity to take the process lead, was partly 'made up for' by virtue of 10nm being a 1.5 node shrink in density. Perhaps, then, the most interesting figure about TSM's N3 is that its pace of improvement (1.7x/2.5yrs) is almost as slow, mathematically, as Intel's 10nm (2.7x/5.0yrs), as 1.7 squared equals 2.9, just a bit higher than Intel's 2.7.
This results in following numbers of density improvement CAGR (annual rate):
- Intel 10nm: 22%
- TMS N3: 23.6%
- Intel 7nm: 40-55%
- Moore's Law: 41%
Of course, all discussion below assumes no delays from either side.
Given that Intel will move to GAA/nanowire at 5nm, this already suggests that its 7nm might not be a bad point of comparison for TSM's N3. And indeed, based on the data we currently have, I project TSM's N3 will be just a little bit better than Intel's 7nm.
However, Intel's 7nm scaling factor seems a bit ambiguous, or contradictory, based on different statements by Intel management it might be 2.0x, so I will interweave a bit of discussion about this. Of course, people will pick the number that suits them best in the absence of final data.
Anyhow, following quote from then-CEO BK in the Q1'18 call makes it clear that 7nm will scale by 2.4x:
As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in [the 10nm] case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.
As Intel discussed at length in its 2017 Technology and Manufacturing Day, 10nm achieved a 2.7x scaling, which Intel called hyperscaling. Intel also introduced a clear, standard density metric, which should make comparisons across the industry possible. As it revealed, according to this metric, 10nm achieved a 100MTr/mm2 density - 100 million transistors per square millimeter. A 2.4x scaling, then, makes for a density of 240MTr/mm2.
The graph below shows WikiChip's numbers for TSM:
This confirms my statement that TSM N3 will be very close to Intel 7nm - N3 has just a 21% higher density. This results in following comparison:
- Intel 7nm: Q4'21, 240MTr/mm2?
- Intel 7nm+: Q4'22?
- TMS N3: Q2'23, 290MTr/mm2
- Intel 5nm: Q4'23? 500MTr/mm2?
Just a few quarters later, at the end of 2023, Intel will move to its 5nm node with a 2x improvement in density.
The graph above shows the extremely long period Intel remained at 14nm, which allowed TSM to leapfrog Intel with the introduction of its own N10 and N7. Intel achieved parity, or a slight edge, with TSM midway TSM's N7 cycle (where we are now), although Intel's 10nm is still quite limited in volume. TSM is charging ahead to 5N later this year but will stay there for a more prolonged time, allowing this time Intel to leapfrog TSM with 7nm and 5nm shortly after 3N.
This means from 7nm onward, Intel will take the process lead back and have the most dense process for the majority after that period; TSM will only have the lead for a few quarters in 2023, by a small margin. This means TSM's four-year process leadership that started in H2'17 will end in H2'21.
However, as I said, there has been some discussion about the exact scaling factor of Intel's 7nm. Some newer information suggests it might be 2.0x. Of course, since BK probably didn't just invent the 2.4x number out of thin air, this implies Intel might have reduced its 7nm targets to this alleged 2.0x factor. Intel, currently, has not provided any guidance as to when it will reveal the details of its 7nm node.
The 2.0x factor would be supported by following information:
• A slide from its 2019 investor meeting said 7nm would feature a 2x scaling factor. This could obviously be explained as only providing one significant digit, as rounding 2.4x would also result in 2x.
• Murthy, December 10, 2019, UBS Global TMT Conference:
So as we've said in the past, we've, we've moved more to a scaling factor around two X between 10 and 7." Again, Murthy is quite vague here with "around 2x".
• Bob Swan, December 3, 2019, Credit Suisse Technology Conference:
Now, the 22 to 14 was not a two times density. It was 2.4, um, the four and it was bumpy along the way, but it worked. And that working gave us the confidence that for 14 to 10, why don't we take the scaling factor up to 2.7. When you do that, the of trying to get more and more density or more and more performance, it's inside the fab. You need more and more revolution in each step inside the fab to deliver that kind of density improvement. (…) So along the way, we, uh, based on our confidence of past performance, we set a higher bar and it didn't work effectively, just took too long. Now good news is we feel like we've got fairly well dialed in. The bad news is it took too long. (…) The criteria is gotta be a more effective balance because customers want products every year. So more effective balances of great performance, but reliable and predictable delivery of new products in an annual, in an annual cadence. (…) Secondly, we're not going to try to do 2.4 scaling or 2.7 scaling. As we think about seven nanometer, you know, we put 2.0 back in line with historical trends as we think about fivenanometer which would be our competitors three nanometers. It's more like 2.0 we're thinking about. So we're not putting as much a challenge on the fab and not taken on so much complexity and design rules, which the more there are, the more complicated, the more complicated it is. So we're capturing these learnings from the past and applying them going forward.
Despite Intel saying in 2018 that 7nm would be a 2.4x scaling, in 2019, apparently, this was reduced to a 2.0x scaling factor, although Murthy, who is responsible for process development among other groups, a week later said it was "around 2x".
In any case, at the lower end of this 2.0-2.4x range, this means 7nm would be a 200MTr/mm2 node. This would give 3nm a more comfortable 50% density uplift but still over a year later. Intel's 5nm with, according to Bob Swan, again a ~2.0x scaling (400MTr/mm2) would follow within a year at the end of 2023 with, in its turn, a noticeable 38% density uplift over TSM N3.
Since ~40% is basically one year of Moore's Law, but Intel would follow within about three quarters, this would give Intel a slight (theoretical) process lead. Practically though, TSM and Intel would be on the same density curve (of initial process introduction, as different companies and kind of chips move to the leading edge at a different pace) but just with different introduction dates. As Intel said, it will have effectively achieved parity at 7nm.
Nevertheless, the pace of improvement seems firmly in Intel's favor, as TSM is on a cadence of at least two years while improving by about 1.7x to 1.9x per generation, while Intel is on a two-year cadence with at least a 2.0x improvement. This would hence give the definite process leadership back to Intel by 5nm: TSM's N2 might be ~520MTr/mm2 in the first half of 2025 compared to Intel's 5nm in late 2023, which would be around 400-480MTr/mm2. (A similar outcome to the scenario I described with the 2.4x scaling factor but just a node later in time.)
Even with this revised information, while Bob Swan compared its 7nm to TSM's N5 and its 5nm to TSM's N3, my analysis shows that Intel might be giving TSM a bit too much credit here, as TSM's N3/N2respectively clearly bear more resemblance to Intel's 7nm/5nm(respectively FinFET/GAA).
Intel, both its CEO Bob Swan and CFO George Davis, also publicly stated Intel is aiming to regain process leadership by 5nm, which my analysis confirms would be the case. (While not in time to market, if Bob Swan compares its 5nm to TSM N3, definitely in terms of density.)
- Intel 7nm: Q4'21, 200MTr/mm2?
- TMS N3: Q2'23, 290MTr/mm2
- Intel 5nm: Q4'23? 400MTr/mm2?
- TSM N2: Q2'25? 520MTr/mm2?
- Intel 3nm: Q4'25? 800MTr/mm2?
In general, the landscape will become much more close/competitive than in the H2'17 to H2'21 time period. For example, Intel's 10nm is still in limited volume despite having theoretical parity at this moment on the curve (20Q2), but Intel said its whole portfolio will move to 7nm in 2022.
Risks
TSM said it has many options in development for N3. As SemiEngineering suggested, TSM could move to nanowire/GAA either at a later stage of N3 or at N2. If TSM, for example, introduces a GAA version of N3 in early 2024, then it won't lag behind Intel's 5nm too much. Of course, this is just speculation for now, but in the 2022 to 2024 timeline, Intel is currently on track to be the leader.
This article is also under the assumption that the companies deliver on their officially stated timelines/roadmaps. For TSM, this means volume production of FinFET N3 in the second half of 2022, which follows N5 which entered volume production in April. For Intel, this means launching the first 7nm product in late 2021 with 2.0-2.4x the density of 10nm, followed by the first 5nm GAA product in late 2023 with ~2.0x the density.
Under that assumption, Intel 10nm is, currently, by a thin margin the most dense process node available. TSM will comfortably take the lead with N5 later this year. Intel will take over the lead with 7nm in late 2021, although by less of a margin than N5 on 10nm. TSM's N3 should be the densest process in early 2023 and 5nm will take over in late 2023.
As one small detail, being a customer of TSM means that Intel should have pretty much as much insight into TSM's next-gen processes as its other customers should have. This could give Intel a slight advantage to know where TSM is heading and more visibility when it is making statements such as recapturing process leadership.
Takeaway
Moore's Law remains of utmost importance at the leading edge of semiconductor chips, as it determines so much of the final product.
The main point here is that TSM's 1.7x scaling target for N3 combined with a 2.5-year cadence implies an annual scaling rate that is almost as poor as what Intel's 10nm achieved inclusive of its delays. This means, for one, that N3 will miss the 2022 Apple (AAPL) iPhone cycle. TSM also retains the FinFET.
As I described, this will let Intel catch up.
Intel, meanwhile, said it is moving back to 2-2.5 year cadence. If Intel's 7nm maintains the 2.4x scaling factor BK described in 2018, then TSM's N3 will be basically a competitor of Intel's 7nm, with a slightly higher density, but Intel's 7nm will launch at least a year earlier.
The picture looks better if Intel's 7nm was dialed down to a 2.0x scaling factor: both companies would be pretty much on the same scaling curve, and hence the leadership crown might change hands a few times.
Still, Intel seems to have a higher pace of improvement: Intel's 5nm will launch a few quarters later, moving to nanowires/GAA and a density that is much higher than N3. Assuming no delays from either side.
TSM benefited hugely from Intel's historic 10nm delay, and N5 just entered production at least a year before Intel's 7nm, but its process leadership days seem numbered.
https://seekingalpha.com/article/43...ng-company-losing-process-leadership-to-intel
